1. Field
Embodiments of the present invention relate to modification of an integrated circuit during a circuit edit. More particularly, the embodiments relate to a system and method for physically depositing an electrically conductive layer to connect circuit edit connection targets in an integrated circuit, and to an integrated circuit containing the layer.
2. Background Information
Newly designed integrated circuits often contain bugs due to errors in the circuit design. A bug represents a portion of an integrated circuit that does not function properly or as desired. A process known as debugging is used to extensively test a fabricated integrated circuit in order to detect and identify these bugs. After a bug is identified, the design of the integrated circuit is modified to eliminate the bug so that the bug will not be formed in subsequently manufactured integrated circuits. By this process of identifying bugs and correcting the design to remove the identified bugs, a final fully-functional integrated circuit design may be obtained and used to mass produce integrated circuits.
Circuit edits are commonly performed during the debugging process so that the debugging process may continue with the affects of the known bug neutralized. A circuit edit involves modifying a previously fabricated integrated circuit having a known bug in order to correct the bug. As an example, once a bug based on a missing connection between interconnect lines is identified, a circuit edit may be performed wherein a layer is deposited by Chemical Vapor Deposition (CVD) in order to connect the two interconnect lines and thereby kill the bug. In this way, the circuit edit may allow a temporary electrical connection to be established between the circuits so that further integrated circuit testing may be performed as if that particular bug never existed. The circuit edit approach is generally regarded as faster and less costly to implement compared with tapeout of a new mask layer and re-fabricating integrated circuits for each identified bug.
FIG. 1 illustrates a CVD layer 160 formed during a circuit edit of the integrated circuit 100. The layer 160 connects a first interconnect 140A and a second interconnect 140B. This connection allows exchange of electrical signals between devices formed within doped regions 120A-B through vias 130A-B, the interconnects 140A-B, and the CVD connection layer 160. Such exchange of electrical signals would not be possible without the layer, due to the dielectric region 150. Accordingly, the layer provides an electrical connection between the first and second doped regions that was not present initially.
The CVD connection layer is formed by milling down through the dielectric to expose the interconnects, depositing gaseous tungsten hexacarbonyl W(CO)6 on and between the exposed interconnects, and then releasing the tungsten atoms from the hexacarbonyl precursor compounds by transferring sufficient energy with a Focused Ion Beam (FIB) to break the tungsten free from the precursor compounds and disperse the precursor to allow deposition of the tungsten. Among the problems associated with layers formed by this process include incomplete removal of the organic precursor compounds.
FIG. 2 shows a sample of material 200 taken from the layer 160. As expected, the sample contains primarily tungsten 210. However, the sample additionally contains other non-tungsten impurities that cause the sample to have a poor electrical conductivity. Organic precursor residuals 220 are one prevalent form of impurity. In this particular example, the organic precursor residuals may include unconverted tungsten hexacarbonyl or carbonyl groups that have failed to disperse. The organic precursor residuals contain carbon that contributes an electrical resistance to the sample. Voids 230 such as bubbles may also be present due to FIB conversion of the layer. Other impurities 240 may also be present and may include derivatives of the organic precursors that have formed under the harsh conditions present during FIB conversion of the organometallic layer.
One significant problem with the impurities is increased electrical resistance. Each of these species provides a significantly greater electrical resistance than tungsten. Depending upon the amount of such impurities, the layer may have an electrical resistivity that may be greater than 160 micro Ohms centimeter, greater than 200 micro Ohms centimeter, or even higher. This is between about 30-35 times the resistivity of pure tungsten, which is about 5.5 micro Ohms centimeters. Such electrical resistances are not desired, particularly when a connection is to be made between interconnects that are spaced widely apart, because the resistances can significantly diminish the electrical signals.